1. Field of the Invention
The present invention relates, in general, to so-called micrologic circuits, that is, logic circuits made by the integrated circuit technique of "condensing" a large number of basic and complex logic functions (logic circuitry) in a single monolithically integrated semiconductor device, according to LSI (Large Scale Integration) or VLSI (Very Large Scale Integration) techniques. According to such techniques a large number of logic elements, as well as complex ones such as binary decades, shift-register, etc., may be implemented on a single chip.
In particular, the invention relates to CMOS logic circuits, i.e. integrated circuits made by the so-called complementary MOS (Metal Oxide Semiconductor) technology, utilizing P-channel and N-channel surface field effect transistors.
Such a "family" of micrologics (CMOS) represents already a great technological improvement with respect to circuits made with MOS transistors of a single polarity (P or N channel) because CMOS circuits have the great advantage of dissipating "power" only during transitions of internal and input and/or output electrical signals. In other words, if DC levels are applied to a CMOS circuit, the circuit, even though correctly supplied, shows a current absorption (defined as I.sub.CC =quiescent supply current or rest current) equaling only to the leakage current of internal junctions of the reverse biased circuit. For SSI (Small Scale Integration) and MSI (Medium Scale Integration) CMOS circuits, i.e. with a total number of transistors which may reach about 500, the I.sub.CC current, under rest conditions, i.e. under static conditions of the signals applied to the inputs (with logic levels of 0 or 1 satisfying the limits of the logic levels V.sub.IL and V.sub.IH) is in the order of EQU I.sub.CC 10.sup.-6 A=1 .mu.A
In more densely packed integrated CMOS circuits of modern LSI or VLSI technologies, such a value may even be reduced by two or three orders of magnitude at room temperature so that the stand-by current, or quiescent current, becomes only a few nanoamperes (nA). As can be easily appreciated, such a characteristic makes the CMOS micrologics extremely advantageous with respect to other families of micrologics and particularly with respect to the one which, because of its extraordinary high speed characteristics, has dominated the field of standard logics (basic logic functions constituting the glue logic or "binder" for aggregating over complex cards LSI or VLSI integrated micrologic devices): that is, the TTL family (Transistor-Transistor Logic). Such TTL micrologics have in fact the disadvantage of a quiescent current which may vary between a few hundred microampers (.mu.A) to a few milliampers (mA).
2. Discussion of the Technical Problem and of the Prior Art
On the other hand, today many apparatuses and/or logic devices made by the CMOS technology are often designed so as to be interfaceable with the output of TTL logic gates. In these instances, the CMOS circuitry is also known as HCT micrologics (from High Speed CMOS, TTL Compatible). In these situations, the gate, i.e. the input stage of the HCT logic, must be capable of accepting and discriminating the worst output levels available from a TTL logic output gate, that is:
1 (TTL logic) equivalent to V.sub.OHTTLmin =2.4 V PA0 0 (TTL logic) equivalent to V.sub.OLTTLmax =0.4 V PA0 V.sub.INHmin =2.0 V and V.sub.INLmax =0.8 V.
with a sufficient noise immunity, so that:
Under these conditions, the triggering threshold voltage for which the input stage of the CMOS logic circuit is designed equals to: ##EQU1##
Normally, such an interface input stage is formed by a pair of complementary push-pull transistors, connected between a supply node and ground, having their respective gates connected in common and constituting the input terminal. In such a configuration the P-channel transistor acts substantially as a load for the N-channel transistor (driver).
A substantially symmetric noise immunity characteristic both for the 0 state and for the 1 state can thus be obtained. However, a problem arises when (as often happens) the whole circuitry stops, i.e. goes in stand-by, on a 2.4 V input level (state 1). In this case, in fact, the input stage of the HCT logic circuit conducts current which is limited only by the sizes of the complementary transistor pairs forming the input stage.
Because HCT logic circuits must be particularly fast, in terms of speed, in order to be compatible with the TTL logic circuits with which they interface, the sizes of the input stage transistors cannot be excessively reduced. As a consequence, in order to maintain the necessary speed, the HCT type CMOS micrologics may show a quiescent current (I.sub.CC) drainage in the order of 1-2 mA, thus losing completely the most important characteristic of CMOS micrologics.
Therefore, one of the technical problems of HCT type CMOS micrologics is that of compromising between high speed and low consumption under rest conditions.
Several solutions have been proposed for overcoming this problem. One of the proposals contemplates the formation of a diode in series with the P-channel transistor of the input stage-with the aim of reducing the quiescent current (I.sub.CC) in the P-channel transistor which, being the element of the input stage subjected to a greater overdrive factor (with 2.4 V at the input), is obviously the critical element to control in order to reduce current drainage.
The second proposal contemplates the utilization of an additional mask for ion implantation in the fabrication process in order to raise the threshold voltage of the P-channel transistor of the input stage with respect to the typical threshold voltage of other integrated transistors. Such proposal does reduce the quiescent current; yet it also depresses the speed characteristics of the logic circuit as a result of the threshold voltage of the P-channel transistor of the input stage being raised.
Both of the known proposals, though allowing a reduction of the quiescent current, decisively reduce the speed of the circuit. Moreover, the second proposal requires an additional masking procedure and therefore is a complex and more costly fabrication process.
A similar problem is encountered when an interface stage must drive a relatively heavy load, such as in the case of a buffer. In this case the load may be of several picofarads (pF) thus requiring an appropriate sizing of the complementary transistor pair of the stage, in order to ensure a sufficient transition speed.
Many problems similar to those already mentioned, or similarly connected problems, are encountered in making multiple inputs CMOS logic circuits, such as for example NAND and NOR circuits and mixed AND-NOR and OR-NAND circuits, etc. In these instances, the primary problem is represented essentially by the necessity of ensuring good noise immunity on all inputs under the various possible configurations. Since this is difficult to obtain by simply refining the control of the triggering thresholds of the integrated devices during the design and fabrication stages, the problem is often overcome by interfacing all the inputs with an appropriate interface stage followed by a second stage for regenerating the phase of the signal i.e. by means of two inverting stages having a configuration similar to the input interface stage of HCT circuits.
Also, in these latter cases, the requirement of preserving a high speed of the circuit often overshadows that of a good discrimination of the triggering threshold under any configuration of the multiple inputs of the circuit.